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24th IEEE International Symposium on On-Line Testing and Robust System Design
(IOLTS'18)
July 2-4, 2018
Hotel Cap Roig, Platja d’Aro, Costa Brava, Spain

http://tima.univ-grenoble-alpes.fr/conferences/iolts/iolts18


“IOLTS 2018 Submissions Site will remain open for Paper Submission till Friday March 2, 2018 AOE (Anywhere-on-Earth).”
CALL FOR PAPERS

Scope

Issues related to On-line testing techniques, and more generally to design for robustness, are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in reliability needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective design for robustness techniques. These needs have increased dramatically with the introduction of nanometer technologies, which impact adversely noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; and make mandatory the use of design for robustness techniques for extending, yield, reliability, and lifetime of modern SoCs. Design for reliability becomes also mandatory for reducing power dissipation, as voltage reduction, often used to reduce power, strongly affects reliability by reducing noise margins and thus the sensitivity to soft-errors and EMI, and by increasing circuit delays and thus the severity of timing faults. There is also a strong relation between Design for Reliability and Design for Security, as security attacks are often fault-based.

The International Symposium on On-Line Testing and Robust System Design (IOLTS), is an established forum for presenting novel ideas and experimental data on these areas. The Symposium is sponsored by the IEEE Council on Electronic Design Automation (CEDA) and the 2018 edition is organized by the IEEE Computer Society Test Technology Technical Council, the University of Athens, and the TIMA Laboratory.

  • The topics of interest include (but are not limited to) the following ones:
  • Quality, yield, reliability and lifespan issues in nanometer technologies
  • Variability, Aging, EMI, and Radiation Effects in nanometer technologies
  • Self-Test and Self-Repair
  • Design-for-Reliability
  • On-line testing techniques for digital, analog and mixed-signal circuits
  • Self-checking circuits and coding theory
  • On-line monitoring of current, temperature, process variations, and aging
  • Self-Healing design
  • Self-Regulating design
  • Self-Adapting design
  • Cross-layer reliability approaches
  • Reliability issues of Low-Power Design
  • Design for Reliability approaches for Low-Power
  • Power density and overheating issues in nanometer technologies
  • Fault-Tolerant and Fail-Safe systems
  • Dependable system design
  • Field Diagnosis, Maintainability, and Reconfiguration
  • Design for Security
  • Fault-based attacks and counter measures
  • Design for Robustness for automotive, railway, avionics, space, large industrial applications, IT infrastructure, cloud computing, and wired, cellular and satellite communications
  • Robustness evaluation
  • CAD for robust circuits design
IEEE Transactions on Device and Materials Reliability (TDRM) Special Issue dedicated to IOLTS 2018: A Special Issue of the prestigious IEEE Transactions is dedicated to IOLTS 2018. Authors of the most highly ranked IOLTS 2018 papers will be invited to submit extended versions of their work shortly after the symposium for review for the Special Issue. Detailed timeline will be announced shortly.     

This year IOLTS puts particular emphasis on the topics of:

  • Robust Automotive Electronics 
    • Design for Robustness is gaining importance in Automotive electronics, due to their stringent Reliability, Security, and Extended Lifespan constraints, which are strongly impacted by the rapidly increasing complexity of automotive electronics and advanced nanometric processes
  • Design for Robustness versus Design for Low-Power
    • Design for Security, as well as Fault Mitigation techniques used for improving Yield, Reliability, and Lifespan, may increase power dissipation. Thus, targeting low-power penalties when developing Design for Robustness approaches is becoming mandatory.
    • Voltage reduction (often used to reduce power), strongly affects yield, reliability, and lifespan, by reducing noise margins and thus the sensitivity to EMI and soft-errors; an by increasing circuit delays and thus the severity of timing faults; as well as by further weakening to the point of failure cells that are weak (due to process variations and aging) but not yet failing.
    • Last but not least, drastic power reduction can be achieved by means of fault mitigation approaches (like those used in Design for Reliability, Yield, and Lifespan techniques); by reducing aggressively the supply voltage and using these approaches to mitigate the failures induced by this reduction.
  • Design for Robustness and Test for Mixed Signal Systems, supported by the Integration of IMSTW at IOLTS
    • For more information about this integration please visit the site: http://tima.univ-grenoble-alpes.fr/conferences/imstw/imstw18/ 

 

 

Submissions

The IOLTS Committee invites authors to submit papers in the above or related technical areas. Accepted papers and posters will be included in formal Proceedings to be published by the IEEE. Papers must be submitted electronically following the instructions provided at the symposium web site. Papers should be in the standard IEEE conferences double-column format. If accepted, regular papers should be allowed six pages in the IEEE proceedings of IOLTS.

Key Dates

Submission deadline: March 2, 2018

Notification of acceptance: March 30, 2018 

Camera-ready papers due: April 23, 2018

Additional Information

Submission Information:

Dimitris Gizopoulos
University of Athens
Athens, Greece
Tel: +30 210 7275145
dgizop@di.uoa.gr

Dan Alexandrescu
iRoC Technologies
Grenoble, France
Tel: +33 (0) 4 38 12 07 63
dan.alexandrescu@iroctech.com

 

General Information:

Michael Nicolaidis
TIMA Laboratory
Grenoble, France
Tel: +33 (0) 4 76 57 46 96
michael.nicolaidis@univ-grenoble-alpes.fr

Antonio Rubio
UPC
Barcelona, Spain
Tel +34  934 017 485     antonio.rubio@upc.edu 

Federative Event on Design for Robustness (FEDfRo): IOLTS’18 is held as part of the 3rd Federative Event on Design for Robustness (FEDfRo). For all details about the event see: http://tima.univ-grenoble-alpes.fr/conferences/fedfro/fedfro18/.

About the location: IOLTS 2018 will be held at Platja d’Aro, Costa Brava, Spain. The area offers a brilliant experience, with so much to offer: a beautiful natural setting, culture, leisure, sport and a delightful seafront location, with an impressive, endless beach, and idyllic little bays. 

 

 



For more information, visit us on the web at: http://tima.univ-grenoble-alpes.fr/conferences/iolts/iolts18

IOLTS’18 is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society-Test Technology Technical Council

TTTC CHAIR
Chen-Huan CHIANG
Intel - USA
E-mail chen-huan.chiang@intel.com

PAST CHAIR
Michael NICOLAIDIS
TIMA laboratory - France
E-mail michael.nicolaidis@imag.fr

TTTC 1ST VICE CHAIR
Matteo SONZA REORDA
Politecnico di Torino - Italy
E-mail matteo.sonzareorda@polito.it

SECRETARY
Joan FIGUERAS
Un. Politec. de Catalunya - Spain
E-mail figueras@eel.upc.es

TEST WEEK COORDINATOR
Yervant ZORIAN
Synopsys, Inc. - USA
E-mail Yervant.Zorian@synopsys.com

TUTORIALS AND EDUCATION
Paolo BERNARDI

Politecnico di Torino
- Italy
E-mail paolo.bernardi@polito.it

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
E-mail rkapur@synopsys.com

EUROPE
Giorgio DI NATALE
LIRMM - France
E-mail giorgio.dinatale@lirmm.fr

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Giorgio DI NATALE
LIRMM - France
E-mail giorgio.dinatale@lirmm.fr

 

PRESIDENT OF BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
E-mail Yervant.Zorian@synopsys.com

SENIOR PAST CHAIR
Adith SINGH
Auburn University – USA
E-mail adsingh@eng.auburn.edu

TTTC 2ND VICE CHAIR
Rohit KAPUR
Synopsys, Inc. – USA
E-mail rkapur@synopsys.com

FINANCE
Chen-Huan CHIANG
Alcatel-Lucent - USA
E-mail chen-huan.chiang@alcatel-lucent.com

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
NAIST - Japan
E-mail k-hatayama@is.naist.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
E-mail champac@inaoep.mx

NORTH AMERICA
André IVANOV
University of British Columbia - Canada
E-mail ivanov@ece.ubc.ca

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
E-mail Yervant.Zorian@synopsys.com


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